Programming and Designing with the 68000 Family: Including the 68000, the 68010/12, the 68020, and the 68030Prentice Hall, 1991 - 641 pàgines The purpose of this book is to provide a complete and in-depth coverage of both hardware and software aspects of designing withe the popular 68000 family of processors. This book introduces the 68000 architecture, and gives an overview and comprehensive comparison of the 68000 family of processors; discusses the assembly language programming; and discusses the hardware design using a 68000 family processor. To fully employ the 68000 family of processors, this book includes information about the family with numerous illustrations bout the architecture, concepts, and th operation of instructions. |
Frases i termes més freqüents
address bus address decode address register address space addressing modes assembly syntax asserted auto-vectored BERR BGACK bit-field bits BKPT breakpoint buffer Bus Control bus cycle bus error bus master bus-error byte cache circuit clock cycles condition codes control signals coprocessor daea data bus data register descriptor destination device displacement DTACK effective address EPROM example exception processing exception vector execution external floating-point format FPCP function codes illustrated in Figure input interface Internal interrupt request long-word loop main memory main processor mantissa microcode Motorola MOVE.W negated nsec number:An NVRAM offset operand operation output page fault parameter peripheral PMMU Program Counter Register Indirect reset shown in Figure specified SRAM stack frame Status Register strobe subroutine synchronous Table transfer valid vector number virtual memory wait-cycles word write cycle XXXX zero