The In-System Configuration Handbook:: A Designer愀 Guide to ISC

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Springer Science & Business Media, 2004 - 201 pàgines
Programmable logic radically changed the electronic system design landscape. It reduced board space needed for random logic, state machines and system interfaces. It allowed faster design cycles, made easy late term bug fixes and gave designers greater freedom to experiment and prototype. In-system programming of these devices has had a similar revolutionary effect. The ability to change the programmed content of programmable logic while it is on the board is equivalent to being able to redesign all the hardware -without changing a single component. This allows the possibility of providing field upgrades of your product to fix problems or to introduce new functionality. It allows designing in reconfiguration as an essential function of your system with different capabilities swapped in as needed during run-time. Further it allows storage of different product profiles for retrieval as necessary to allow just-in-time configuration of systems to meet market needs. Recent developments in programmable logic have helped in making realizing reconfigurable systems more streamlined. The most significant development, though, was the introduction, approval and popularization of IEEE STD 1532, the IEEE Standard for In-System Configuration of Programmable Devices. The purpose of this text is to bring together, in a single volume, the information needed by systems designers to develop applications that include configurability. This covers the entire range of systems from the The In-System Configuration Handbook simplest implementations that merely include configurable logic to realize system functions to the most complicated that include reconfigurability as part of the application itself.
 

Continguts

A Brief History of InSystem Configuration
1
211 Lattice Semiconductor and InSystem Programming
3
3 Standard Approaches
5
CONFIGURABLE DEVICE ARCHITECTURES
14
21 Simple Complex Programmable Logic Devices
15
211 Altera CPLD Architectures
19
212 Lattice Semiconductor CPLD Architectures
20
213 Xilinx CPLD Architectures
22
119 ISC_Procedure
114
1110 ISC_Action
115
1111 The ISC_Illegal_Exit Attribute
116
13 Using the IEEE STD 1532 BSDL File
127
2 Comparative Evaluation of Approaches
133
The IEEE STD 1532 Compliant Device
138
3 System Pins
140
4 Algorithmic Operation
141

22 Field Programmable Gate Arrays
23
Xilinx FPGA Architectures
24
222 Actel FPGA Architectures
28
223 Altera FPGA Architectures
30
INSYSTEM CONFIGURATION TECHNOLOGIES
32
Nonvolatile Configuration Technologies
33
22 Electrically Erasable and Programmable Cells
35
23 Flash Erasable and Programmable Cells
37
24 Volatile Configuration Technologies
39
3 Configuration Access Ports
41
31 Parallel Access
42
32 Serial Access
45
CONFIGURATION DESCRIPTION AND SPECIFICATION LANGUAGES
48
2 JEDEC Standard Data Transfer Format
49
21 Basic File Organization
50
212 The C Field
51
CONFIGURATION DESCRIPTION AND SPECIFICATION LANGUAGES
53
112 The SDR Command
55
113 The RUNTEST Command
56
114 Other Commands
57
2 STAPL Standard Test and Programming Language
59
22 STAPL File Example
61
23 Using STAPL Files
63
CONFIGURATION DESCRIPTION AND SPECIFICATION LANGUAGES
66
12 Where did Java come from?
67
13 Java and the World Wide Web
69
15 Development of Java API for BoundaryScan
70
16 Basic Java API for BoundaryScan File Structure
71
161 The API Components
72
1612 The javaScanBitlf Interface Class
73
1613 The javaScanHWIf Interface Class
74
1614 Tbe javaScanOperations Class
75
162 Data Compression
77
18 Using the Java API for BoundaryScan
97
CONFIGURATION SPECIFICATION AND DESCRIPTION LANGUAGES
100
11 Basic IEEE STD 1532 BSDL File Structure
101
111 IEEE STD 11491 BSDL Attributes
102
112 The ISC_Pin_Behavior Attribute
103
113 The ISC_Fixed_System_Pins Attribute
104
114 The ISC_Status Attribute
106
116 The ISC_Security Attribute
107
117 Description of ISC Algorithms in the BSDL File
109
42 Algorithm Optimizations
142
43 Proprietary Algorithm Support
144
46 Asynchronous Transitions to Test Logic Reset
145
48 Device Operation Success Indication
146
5 Summary
147
DESIGN CONSIDERATIONS FOR INSYSTEM CONFIGURABLE SYSTEMS
148
21 IEEE STD 1532 Compliance
149
22 Power consumption during configuration
150
23 Configuration Speed
151
24 Endurance
152
26 Security
153
29 Configuration Process Validation
154
3 Signal Layout Considerations
155
4 System Power Considerations
159
5 Device and System Test Considerations
160
6 System Configurability Considerations
161
62 Production Configuration
162
631 Field Upgradeable Service Engineer
163
64 BiConfigurable
164
65 Functionally Reconfigurable
165
66 Medley Reconfigurable
166
INSYSTEM CONFIGURATIONBASED PLATFORMS
168
12 Manufacturing
169
13 Field
170
21 PLD Manufacturer Specialty Tools
171
212 Lattice Semiconductor ispVM
172
22 PCbased BoundaryScan Tools
173
3 Automatic Board Test Equipment Tools
174
4 Field Application Tools
176
41 Direct TAP Access Methods
177
DESIGNING INSYSTEM CONFIGURABLE APPLICATIONS
180
2 Designing for Simple Configurability
181
3 Designing for Field Reconfigurability
185
31 Designing for Network Reconfigurability
186
4 Designing For Periodic Reconfigurability
188
6 Designing for Runtime Reconflgurability
189
7 Summary
193
Conclusion
References
Index
Copyright

Altres edicions - Mostra-ho tot

The In-System Configuration Handbook:: A Designer’s Guide to ISC
Neil G. Jacobson
Previsualització limitada - 2012
The In-System Configuration Handbook:: A Designer’s Guide to ISC
Neil G. Jacobson
Previsualització no disponible - 2012
The In-System Configuration Handbook
Neil G Jacobson
Previsualització no disponible - 2003

Frases i termes més freqüents

Actel allows antifuse application approach architecture array attribute basic BC_1 boundary-scan BSDL file clock compliant devices configurable devices configurable system configuration algorithm configuration data configuration port connected CPLD data compression data register data shift defined device configuration device's EEPROM EEPROM cell embedded systems erase FAKE_1532_DEVICE field upgrade floating gate flow format FPGA functionality IDCODE value IEEE STD in-system configuration In-System Programming input instruction register interconnect interface ISC data file ISC_ADDRESS_SHIFT ISC_DATA_SHIFT ISC_DISABLE ISC_NOOP ISC_PROGRAM ispVM JAPIBS JEDEC file Lattice Semiconductor loaded LOGIC BLOCK manufacturers method microseconds msec nonvolatile devices operation output private static xilinxCpldBits processor PROGRAMMABLE DEVICE programmable logic devices proprietary reconfiguration Run Test/Idle serial Shift DR signals specific SRAM standard STAPL file STD 1532 compliant SVF files system configuration TAP controller target transistor transitions typically update USERCODE vendors VHDL volatile devices voltage wait TCK Xilinx

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Informació bibliogràfica

TítolThe In-System Configuration Handbook:: A Designer愀 Guide to ISC
AutorNeil G. Jacobson
Edicióil·lustrada
EditorSpringer Science & Business Media, 2004
ISBN140207655X, 9781402076558
Nre. de pàgines201 pàgines
  
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